Products Finishing

SEP 2015

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PRODUCTS FINISHING — pfonline.com 21 PLATING LED LIGHTS Being Flexible in a Rigid Plating World By Michael Carano, RBP Chemical Technology With double-digit growth in the foreseeable future, fexible printed circuits (FPC) have found a tremendous niche as an enabler for various electronic applications. This trend is expected to drive the need to increase productivity while improving performance and reducing costs. Of course, in order to sell FPC, one must tackle the unenviable task of metalizing these ofen dificult-to-plate materials. In particular, the deposition of metal on a polyimide flm is ofen discussed. When speaking about adhesion of a deposited metal to a substrate, there are two distinct but related processes: the frst relates to surface preparation conditioning, and the second to the deposition of the metal itself. One theme electroplaters ofen hear is surface preparation. Because materials such as polyimide are prone to low copper adhesion, specially formulated conditioners are used to provide an adhesion-conducive surface. Every surface receiving coating requires activation. Without it, defects are ofen found, include blistering, peeling and voids. One critical step in the process sequence is to use a conditioning agent—prior to electroless copper metallization— that makes the polyimide material more susceptible to adhesion of the palladium catalyst. In turn, the conditioning agent enhances the adhesion of the subsequently plated copper to the polyimide. Second Conditioning Step Electroless copper plating process systems ofen include a second conditioning step afer polyimide etch. Although I recommend such a step, it is with reservation. Basically, the second conditioning step must contain materials that are free rinsing so as to not leave a flm on the polyimide that would reduce adhesion of the copper deposit. Should such a situation arise, the fabricator would be better served to run three performance tests—one with no extra conditioner, one with 50 percent of the recommended concentration and one with the full recommendation. Then, afer plating, perform a tape test to quantify the adhesion, or lack thereof. The importance of the conditioning step notwithstanding, total success is not achievable without a low stress electroless copper deposit. Typically, deposited metals exhibiting a high degree of internal stress fnd it necessary to pull away from the substrate in order to relieve the stress condition. Good Interconnect Reliability Literature reviews and research studies provide evidence that the grain structure of the copper deposit infuences the deposit's adhesion to the copper interconnect. Microsections taken from test boards processed in diferent electroless copper process formulations show vastly varying structures. In Figure 1, the structure is a fnely grained crystal structure that appears "loose." In testing, this type of structure was more prone to hole-wall pull away and overall poor adhesion. In Figure 2, the structure has a high correlation to good interconnect reliability (determined by IST and thermal shock testing), exhibits very low stress and provides excellent adhesion when subjected to tape testing. It is highly recommended that maximum copper adhesion be achieved for fex circuit applications. Further, the data supports the assertion that a low- to medium-deposition electroless copper process be employed for fexible circuit manufacturing. These types of electroless copper processes typically provide a low stress deposit with a fairly large grain structure. This is not to say that direct metallization processes are not compatible with fex circuit fabrication. On the contrary, direct metallization is very profcient with respect to fex. Michael Carano is with RBP Chemical Technology. He has been involved in the PWB, general metal finishing photovol- taic industries for nearly 30 years and is co-chair of the IPC Technology Roadmap Executive Committee. Carano holds nine U.S. patents in topics including plating, metallization processes and PWB fabrication techniques. Figure 1 Figure 2

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